Mobile RF communication systems are trending towards smaller cell sizes and more power amplifiers with lower power, e.g. 5G (5th generation) mobile networks, wireless systems and MIMO (multiple input, multiple output) systems, etc. Physical space requirements can be reduced by integrating more parts of the system. For the RF power amplifier, this means significant challenges in both efficiency and linearity. Modern high-power technologies such as GaN and LDMOS (Laterally Diffused MOSFET) offer superior efficiency performance, but impose serious challenges in terms of linearity. Accordingly, trade-offs such as gain/loss versus linearity must be made.
Conventional interstage matching networks for coupling the final stage of an RF communication system to a driver stage are typically designed to transform the gate input impedance of the final stage to a specific load impedance for the driver. Traditionally, the phase of the interstage matching network is ignored in the design process since the phase of the interstage matching network does not matter for a final stage having a constant or nearly constant input impedance. However, higher power and higher frequency semiconductor technologies such as GaN have an input impedance that varies significantly with input power, causing a large variation in the load impedance for the driver and hence changing gain and phase significantly. An improved interstage matching network suited for high performance semiconductor technologies is needed.